Method and system for parametric reduction of sequential designs

ABSTRACT

A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is related to the following co-pending U.S.patent applications filed on even date herewith, and incorporated hereinby reference in their entirety:

Ser. No. 11/______ (AUS920050292US1), entitled “METHOD AND SYSTEM FORREVERSING THE EFFECTS OF SEQUENTIAL REPARAMETERIZATION ON TRACES”;

Ser. No. 11/______ (AUS920050293US1), entitled “METHOD FOR PRESERVINGCONSTRAINTS DURING SEQUENTIAL REPARAMETERIZATION”;

Ser. No. 11/______ (AUS920050294US 1), entitled “METHOD FOR HEURISTICPRESERVATION OF CRITICAL INPUTS DURING SEQUENTIAL REPARAMETERIZATION”;and

Ser. No. 11/______ (AUS920050295US1), entitled “METHOD FOR OPTIMALSYNTHESIS OF BINARY DECISION DIAGRAMS WITH INVERTED EDGES ANDQUANTIFIABLE AS WELL AS NONQUANTIFIABLE VARIABLES”.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to verifying designs and inparticular to representing a logic function in a decision diagram. Stillmore particularly, the present invention relates to a system, method andcomputer program product for performing parametric reduction ofsequential designs.

2. Description of the Related Art

With the increasing penetration of processor-based systems into everyfacet of human activity, demands have increased on the processor andapplication-specific integrated circuit (ASIC) development andproduction community to produce systems that are free from design flaws.Circuit products, including microprocessors, digital signal and otherspecial-purpose processors, and ASICs, have become involved in theperformance of a vast array of critical functions, and the involvementof microprocessors in the important tasks of daily life has heightenedthe expectation of error-free and flaw-free design. Whether the impactof errors in design would be measured in human lives or in mere dollarsand cents, consumers of circuit products have lost tolerance for resultspolluted by design errors. Consumers will not tolerate, by way ofexample, miscalculations on the floor of the stock exchange, in themedical devices that support human life, or in the computers thatcontrol their automobiles. All of these activities represent areas wherethe need for reliable circuit results has risen to a mission-criticalconcern.

In response to the increasing need for reliable, error-free designs, theprocessor and ASIC design and development community has developedrigorous, if incredibly expensive, methods for testing and verificationfor demonstrating the correctness of a design. The task of hardwareverification has become one of the most important and time-consumingaspects of the design process.

Among the available verification techniques, formal and semiformalverification techniques are powerful tools for the construction ofcorrect logic designs. Formal and semiformal verification techniquesoffer the opportunity to expose some of the probabilistically uncommonscenarios that may result in a functional design failure, and frequentlyoffer the opportunity to prove that the design is correct (i.e., that nofailing scenario exists).

Unfortunately, the resources needed for formal verification, or anyverification, of designs are proportional to design size. Formalverification techniques require computational resources which areexponential with respect to the design under test. Similarly, simulationscales polynomially and emulators are gated in their capacity by designsize and maximum logic depth. Semi-formal verification techniquesleverage formal methods on larger designs by applying them only in aresource-bounded manner, though at the expense of incompleteverification coverage. Generally, coverage decreases as design sizeincreases.

One commonly-used approach to formal and semiformal analysis forapplications operating on representations of circuit structures is torepresent the underlying logical problem structurally (as a circuitgraph), and then use Binary Decision Diagrams (BDDs) to convert thestructural representation into a functionally canonical form. In such anapproach, in which a logical problem is represented structurally andbinary decision diagrams are used to convert the structuralrepresentation into a functionally canonical form, a set of nodes forwhich binary decision diagrams are required to be built, called “sink”nodes, is identified. Examples of sink nodes include the output node ornodes in an equivalence checking or a false-paths analysis context.Examples of sink nodes also include targets in a property-checking ormodel-checking context.

Techniques for reducing the size of a design representation have becomecritical in numerous applications. Logic synthesis optimizationtechniques are employed to attempt to render smaller designs to enhancechip fabrication processes. Numerous techniques have been proposed forreducing the size of a structural design representation. For example,redundancy removal techniques attempt to identify gates in the designwhich have the same function, and merge one onto the other. Suchtechniques tend to rely upon binary decision diagram-based or Booleansatisfiability-based analysis to prove redundancy, which tend to becomputationally expensive.

What is needed is a method for reducing the complexity of verificationby reducing the number of gates in a design under verification.

SUMMARY OF THE INVENTION

A method, system and computer program product for performing parametricreduction of sequential designs is disclosed. The method comprisesreceiving an initial design including one or more primary inputs, one ormore targets, and one or more state elements. A cut of the initialdesign including one or more cut gates is identified, and a relation ofone or more values producible to the one or more cut gates in terms ofthe one or more primary inputs and the one or more state elements iscomputed. The relation is synthesized to form a gate set, and anabstracted design is formed from the gate set. Verification is performedon the abstracted design to generate verification results.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objects and advantages thereof, willbest be understood by reference to the following detailed descriptionsof an illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 depicts a block diagram of a general-purpose data processingsystem with which the present invention of a method, system and computerprogram product for performing parametric reduction of sequentialdesigns may be performed;

FIG. 2 is a high-level logical flowchart of a process for performingparametric reduction of sequential designs in accordance with analternative embodiment of the present invention;

FIG. 3 is a high-level logical flowchart of a process for performingparametric reduction of sequential designs in accordance with apreferred embodiment of the present invention;

FIG. 4 is a high-level logical flowchart of a process for preservationof constraints during sequential reparameterization in accordance with apreferred embodiment of the present invention;

FIG. 5 is a high-level logical flowchart of a process for performingoptimal synthesis of binary decision diagrams with inverted edges andquantifiable as well as nonquantifiable variables in accordance with apreferred embodiment of the present invention;

FIG. 6 is a high-level logical flowchart of a process for performingreversal of the effects of sequential reparameterization on traces inaccordance with a preferred embodiment of the present invention; and

FIG. 7 is a high-level logical flowchart of a process for performingheuristic preservation of critical inputs during sequentialreparameterization in accordance with a preferred embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides a method, system, and computer programproduct for parametric reduction of a structural design representation.As will be explained below, the present invention identifies a candidateset of gates of a netlist representation, particularly, a cut of anetlist graph, to attempt to re-encode. The present invention thencreates a behaviorally equivalent piece of logic, and replaces theoriginal cut with this new piece of logic, i.e., the present inventionreplaces each cut gate in the original design by a gate in thereplacement logic.

With reference now to the figures, and in particular with reference toFIG. 1, a block diagram of a general-purpose data processing system, inaccordance with a preferred embodiment of the present invention, isdepicted. Data processing system 100 contains a processing storage unit(e.g., RAM 102) and a processor 104. Data processing system 100 alsoincludes non-volatile storage 106 such as a hard disk drive or otherdirect-access storage device. An Input/Output (I/O) controller 108provides connectivity to a network 110 through a wired or wireless link,such as a network cable 112. I/O controller 108 also connects to userI/O devices 114 such as a keyboard, a display device, a mouse, or aprinter through wired or wireless link 116, such as cables or aradio-frequency connection. System interconnect 118 connects processor104, RAM 102, storage 106, and I/O controller 108.

Within RAM 102, data processing system 100 stores several items of dataand instructions while operating in accordance with a preferredembodiment of the present invention. These include an initial design (D)netlist 120, a binary decision diagram builder 126 and an output table122 for interaction with a verification environment 124. In theembodiment shown in FIG. 1, initial design (D) netlist 120 containstargets (T) 134 state elements (R) 136 and primary inputs (I) 138. Otherapplications 128 and verification environment 124 interface withprocessor 104, RAM 102, I/O control 108, and storage 106 throughoperating system 130. One skilled in the data processing arts willquickly realize that additional components of data processing system 100may be added to or substituted for those shown without departing fromthe scope of the present invention. Other data structures in RAM 102include binary decision diagrams 170, cut gates 132, cutpoints 140,relation (S) 142, abstracted design (D′) 144, gate set (C″) 146,corresponding gates (U′) 148, trace (P″) 150, abstracted trace (P′) 152,unabstracted trace (P) 154, set (C′) 176, constraint gates in cut gates(BU) 180, set (B′) 182 and new trace (p) 178.

A netlist, such as design (D) netlist 120, is a popular means ofcompactly representing problems derived from circuit structures in thecomputer-aided design of digital circuits. Such a representation isnon-canonical and offers the ability to analyze the function from thenodes in the graph. Initial design (D) netlist 120, contains a directedgraph with vertices representing gates and edges representinginterconnections between those gates. The gates have associatedfunctions, such as constants, primary inputs (I) 138 (e.g. RANDOM gates,which deliver random values at the given input), combinational logic(e.g., AND gates), and sequential elements (hereafter referred to asregisters). Registers have two associated components; their next-statefunctions and their initial-value functions, which are represented asother gates in the graph. Certain gates in the netlist may be labeled asprimary outputs (O) 162, invariants (N) 164, targets (T) 134 andconstraints (B) 160.

Semantically, for a given register, the value appearing at itsinitial-value gate at time “0” (“initialization” or “reset” time) willbe applied by verification environment 124 as the value of the registeritself; the value appearing at its next-state function gate at time “i”will be applied to the register itself at time “i+1”. Certain gates arelabeled as targets (T) 134 or constraints (B) 160. Targets (T) 134correlate to the properties that require verification. Constraints (B)160 are used to artificially limit the stimulus that can be applied tothe RANDOM gates of initial design (D) netlist 120; in particular, whensearching for a way to drive a “1” to a target (T) 134, the verificationenvironment 124 must adhere to rules such as, for purpose of example,that “every constraints (B) 160 gate must evaluate to a logical 1 forevery time-step” or “every constraints (B) 160 gate must evaluate to alogical 1 for every time-step up to, and including, the time-step atwhich the target is asserted.” For example, in verification environment124, a constraints (B) 160 could be added which drives a 1 exactly whena vector of RANDOM gates to simulate even parity. Without itsconstraints (B) 160, the verification environment 124 would considervaluations with even or odd parity to those RANDOM gates; with theconstraints (B) 160, only even parity would be explored.

Invariants (N) 164 are similar to constraints in the sense that theywill always evaluate to a “I”. However, unlike constraints (B) 160, theywill naturally evaluate to a 1 even if discarded from the problemformulation (i.e., they are redundant facts about the way the designwill behave due to its structural definition). These redundant facts maybe useful in formal verification to obtain proofs of correctness. Forexample, an invariant (N) 164 node could assert that a set of registersalways evaluates to even parity; that fact may help the performance ofproof-based techniques.

Processor 104 executes instructions from programs, often stored in RAM102, in the course of performing the present invention. In a preferredembodiment of the present invention, processor 104 executes verificationenvironment 124. Verification environment 124 contains a parametricreduction toolkit 166, including a selection unit 156, a replacementunit 158, a translation unit 168, exploitation unit 172 and bias unit174.

Initial design (D) netlist 120 includes replaceable gates and gateswithin the cone of influence of each replaceable gate. For example,assume the existence within initial design (D) netlist 120 ofreplaceable gates G1 and G2, each of which has a cone of influenceincluding combinational logic as well as registers. Parametric reductiontoolkit 166 is tuned to abstract logic within initial design (D) netlist120 which is combinationally driven by RANDOM gates, and hence is lesslikely to abstract any logic within initial design (D) netlist 120 whichis not combinationally driven by RANDOM gates. When performing anabstraction to replace gates G1 and G2 within initial design (D) netlist120, parametric reduction toolkit 166 will replace gates on thefanin-side of a cut at cutpoint 140, such that gates within initialdesign (D) netlist 120 in the fanout-side of the cut at cutpoint 140 arenot modified by parametric reduction toolkit 166 when performing theabstraction, and there is a 1:1 mapping between such gates in thefanout-side of the cut at cutpoint 140 within initial design (D) netlist120 and abstracted design (D′) 144. Note also that there is a uniquemapping from gates on the cut at cutpoint 140 within initial design (D)netlist 120 and abstracted design (D′) 144.

The abstraction performed by parametric reduction toolkit 166 togenerate abstracted design (D′) 144 results in a trace-equivalencebetween initial design (D) netlist 120 and abstracted design (D′) 144.Trace equivalence between two designs requires that, first, for allpossible traces (sequences of values to gates over time) over all gatesof initial design (D) netlist 120 on the cut at cutpoint 140 and in thefanout-side of the cut at cutpoint 140 and, second, for all possibletraces over the gates in gate set (C″) 146 which are to replace cutgates (U) 132 and over the gates in the fanout-side of the cut atcutpoint 140 in abstracted design (D′) 144, for every trace in theformer, there exists an equivalent trace in the latter, and vice-versa.The sequences of values producible to a selected set of gates of initialdesign (D) netlist 120 is identical to the sequence of values producibleto the corresponding gates in the abstracted design (D′) 144.

Parametric reduction toolkit 166 is explicitly tuned for reducing thenumber of RANDOM gates in abstracted design (D′) 144, and heuristicallyis able to eliminate other gates. As a result, parametric reductiontoolkit 166 has the ability to exponentially improve the run-time ofautomated formal verification tools within verification environment 124with respect to the state-of-the-art possible without this approach, andalso provide benefits to other methods such as simulation, emulation,and other design reasoning/optimization paradigms.

Parametric reduction toolkit 166 provides selection unit 156 to choosecandidate cut gates (U) 132 for abstraction, as well as replacement unit158, for symbolically analyzing and synthesizing gate set (C″) 146. Whencombined, selection unit 156 and replacement unit 158 prevent theexponential degradation of the performance of parametric reductiontoolkit 166 as the size of the set of cut gates (U) 132 being replacedincreases. Exponential degradation of the performance of explicitanalysis, such as simulation-based analysis, is typical of the problemsof the prior art. Gate set (C″) 146 can be guaranteed to require at most‘N’ RANDOM gates for a cut of ‘N’ gates. By selecting a set of cut gates(U) 132 with minimal size, parametric reduction toolkit 166 may achievea maximal reduction in RANDOM gates.

Selection unit 156 is utilized for selecting the cut gates to attempt toabstract. Parametric reduction toolkit 166 reduces RANDOM gate count.Using replacement unit 158, discussed below, parametric reductiontoolkit 166 replaces logic for a set of ‘N’ cut gates with a set of newRANDOM gates that will include at most ‘N’ new gates. Thus, parametricreduction toolkit 166 attempts to select as small of a set of gates toabstract as possible that constitutes a “cut” over as many RANDOM gatesin original design (D) netlist 120 as possible.

The operation of selection unit 156 is more easily understood withrespect to a set of requirements in the choice of a cut at a cutpoint140 of original design (D) netlist 120. A cut at a cutpoint 140 oforiginal design (D) netlist 120 is a partition of its gates into twosets: the fanin-side, and the fanout-side. Parametric reduction toolkit166 computes a cut at a cutpoint 140 of original design (D) netlist 120,then replaces the fanin-side with a new and simpler piece of logic. Thisreplacement is performed by reconnecting the cut gates (U) 132 whichsource edges which cross from the fanin side to the fanout side withsource gates in the new logic. Parametric reduction toolkit 166 attemptsto ensure that all invariants (N) 164, targets (T) 134 and constraints(B) 160 will be in the fanout-side of the cut at cutpoint 140, such thatthe original fanin-side of the cut at cutpoint 140 will be eliminatedfrom the cone-of-influence of the problem (defined as all logic whichfans out to the invariants (N) 164, targets (T) 134 and constraints (B)160) when parametric reduction toolkit 166 reconnects to the new logic.

Selection unit 156 additionally attempts to find a cut at cutpoint 140which has as few cut gates (U) 132 as possible, because the gate set(C″) 146 created in replacement unit 158 requires one RANDOM gate percut gate (U) 132. Selection unit 156 selects cutpoints 140 using min-cutanalysis in several steps. First, selection unit 156 labels eachinvariant (N) 164, target (T) 134 and constraint (B) 160 gate oforiginal design (D) netlist 120 as a “sink”. Selection unit 156 thenlabels every next-state and initial-value gate as a sink. The failure tolabel every next-state and initial-value gate as a sink might preventselection unit 156 from obtaining a cut at a cutpoint 140 of the graphwhose fanin-side will fall out of the cone of influence when replaced(due to the mapping of registers to initial-value and next-statefunction gates). Additionally selection unit 156 labels every next-stateand initial-value gate as a sink, because replacement unit 158 does notexplicitly seek to re-encode the sequential behavior of the design.

Selection unit 156 then labels every RANDOM gate as a source. Finally,selection unit 156 utilizes min-cut analysis between the labeled sourcesand sinks to find a minimal set of cut nodes at cutpoint 140. Selectionunit 156 seeks a cut at a cutpoint 140 which has minimal size withrespect to the number of gates sourcing crossing edges of the cut. Notethat the min-cut analysis of selection unit 156 is combinational in thesense that it does not traverse “through” next-state functions orinitial-value functions of registers. The combinational operation ofselection unit 156 is well-suited to the process of maximizing RANDOMgate reduction potential. In the case that multiple min-cuts ofidentical width exist, parametric reduction toolkit 166 may attempt toabstract any or all of them to find the solution with greatest reductionpotential.

As will be discussed with respect to replacement unit 158, parametricreduction toolkit 166 relies upon the ability to identify all possiblevalues producible on cut gates (U) 132 as a function of any registersthat may appear in the cone of influence of the cut gates (U) 132, thenre-encoding the fanin-side of the cut at cutpoint 140 using a new set ofRANDOM gates. The min-cut result as seeded is ideally suited in thisapplication since it will compute the smallest available cut of cutgates (U) 132, including the most original RANDOM gates. As an example,consider a set of seven selected cut gates which originally has 20RANDOM gates in its fanin-side. After replacing the fanin-side of thecut with the gate set (C″) 146, replacement unit 158 can produce a gateset (C″) 146 with only seven new RANDOM gates.

Note, however, that the methods used by selection unit 156 to analyzeand by replacement unit 158 to replace the set of cut gates (U) 132 maybe computationally expensive, and it may be the case that replacementunit 158 cannot succeed in processing the set of cut gates (U) 132chosen by selection unit 156. Parametric reduction toolkit 166 solvesthis problem incrementally, by performing the analysis and replacementin a levelized fashion. Parametric reduction toolkit 166 defines thelevel of gates such that all constant gates, RANDOM gates, and registershave level 0; the level of other combinational gates is equal to themaximum level of any of their sourcing gates plus one. Parametricreduction toolkit 166 iterates between level 1 and the maximum level ofany of the chosen “ideal” cut gates (U) 132 at cutpoints 140, solving amin-cut problem involving all gates of the given level and the RANDOMgates in their cone of influence. At each stage, the parametricreduction toolkit 166 analyzes and abstracts the smaller, partial coneof logic.

One benefit of the incremental solution described above is that earlierstages of abstraction by selection unit 156 and replacement unit 158simplify the logic to be analyzed and abstracted in later stages, withthe result that earlier stages reduce the resources needed by the laterstages. This reduces overall peak resource requirements, and increasesthe chances that the desired cut may be successfully abstracted in anincremental fashion even if this abstraction is computationallyinfeasible without incremental processing. Further, even if the processemployed by selection unit 156 and replacement unit 158 ultimately failsto abstract the desired cut gates (U) 132 due to resource limitations,it is likely that a fair amount of simplification can still besuccessfully performed on earlier stages. If applied using atransformation-based verification toolset, which may be included inverification environment 124, further transformations are possiblebetween each incremental abstraction, which may further simplifyabstracted design (D′) 144 to enable greater reductions.

Parametric reduction toolkit 166 first process the gates at ahypothetical first level, abstracting the gates at that level withsimpler logic. Parametric reduction toolkit 166 then processes the gatesat a hypothetical second level; this processing includes the simplified,replaced logic for at the hypothetical first level obtained during theprior step. Parametric reduction toolkit 166 then process the gates at ahypothetical third level, and so on; eventually, processing the logicwith the highest-level of any gate in the originally selected min-cut.Parametric reduction toolkit 166 may perform all necessary reductions ina single step, though the reduction may be more computationallyefficient in the incremental manner as discussed. Alternativeembodiments of this method are possible, such as starting/stopping at alevel other than the minimum and the maximum level of any gate in theoriginally selected min-cut. Incrementing by M levels rather than by 1is also possible. The latter alternative embodiment may prove useful incases in which the number of levels is very large, to reduce the numberof distinct abstraction steps.

Replacement unit 158 analyzes the cut at cutpoint 140, and creates gateset (C″) 146. Replacement unit 158 creates gate set (C″) 146 so thateach original cut gate (U) 132 will be replaced by one gate in gate set(C″) 146. In order to facilitate this one-to-one mapping, replacementunit 158 adheres to the requirement that the set of values which may beproduced by the gate set (C″) 146 must be identical to set of valueswhich may be produced by the original cut gates (U) 132 on a per-statebasis. For every state (valuation to registers) of original design (D)netlist 120, the replacement unit 158 enumerates the subset of the 2ˆN(for N cut gates, where symbol ˆ denotes exponentiation) possible valueswhich may be produced at those cut gates (U) 132 under some valuation tothe original RANDOM gates. The subset of 2ˆN possible values to thereplacement gate set (C″) 146 for cut gates (U) 132 (under somevaluation to the new RANDOM gates) must equal that of the original cutgates (U) 132, on a per-state basis. Note that replacement unit 158 usesthe same set of registers in both the original design (D) netlist 120and abstracted design (D′) 144, ensuring that the replacement with gateset (C″) 146 preserves property checking (i.e., replacement with gateset (C″) 146 will not render incorrect ‘pass’ nor ‘fail’ results) whenthe target (T) 134 constraint (B) 160 and invariant gates (N) 164 are inthe fanout-side of the logic being replaced.

Replacement unit 158 utilizes binary decision builder 126 and binarydecision diagrams 170 to avoid bottlenecks in the enumeration processdescribed above (e.g., analyzing 2ˆ N values one-at-a-time in a netlistbecomes infeasible as N grows beyond 30). The operation of replacementunit 158 in enumerating the producible values at cut gates (U) 132 isdiscussed below. In the discussion below, C_(‘)i represents the i'th cutgate. Replacement unit 158 declares a distinct binary decision diagram170 variable for each cut gate (U) 132 (hereafter called G_i) atcutpoints 140; for each RANDOM gate in the fanin-side of the cut atcutpoint 140; and for each register in the fanin-side of the cut atcutpoint 140. Replacement unit 158 builds a binary decision diagram 170for the function of each cut gate (U) 132 (hereafter called F_i)supported by the binary decision diagrams 170 variables for the RANDOMgates and registers. Replacement unit 158 next builds binary decisiondiagrams 170 for the expression (G_i==F_i), conjuncts this expressionover all i's, and then existentially quantifies the RANDOM gatevariables from the conjunction. The resulting binary decision diagrams170 comprise all possible valuations to the cut gates (U) 132(represented by the G_i's) as a function of the registers (representedby their corresponding binary decision diagram 170 variables).

With reference now to FIG. 3, a high-level logical flowchart of aprocess for performing parametric reduction of sequential designs inaccordance with a preferred embodiment of the present invention isillustrated. The process starts at step 300 and then proceeds to step302, which depicts verification environment 124 receiving initial design(D) netlist 120, including targets (T) 134, state elements (R) 136 andprimary inputs (I) 138. The process next moves to step 304. At step 304,selection unit 156 identifies cut points 140 for a cut (C, C′) ofinitial design (D) netlist 120 where (C′) is a superset of targets (T)134, letting cut gates (U) 132 represent the cut gates sourcing edgesfrom (C) to (C′).

The process then proceeds to step 306, which depicts replacement unit158 computing the relation (S) 142 of values producible to (I, R, U),then existentially quantifying primary inputs (I) 138 from relation (S)142, resulting in a relation (S) 142 from state elements (R) 136 to cutgates (U) 132. The process then moves to step 308. At step 308,replacement unit 158 synthesizes relation (S) 142 as a function fromstate elements (R) 136 to cut gates (U) 132, forming gate set (C″) 146.The process proceeds to step 310 which depicts replacement unit 158forming abstracted design (D′) 144 equal to (C″, C′). Correspondinggates (U′) 148 represent the gates in gate set (C″) 146 corresponding tocut gates (U) 132 in constraints (B) 160. The process then proceeds tostep 312, which depicts verification environment 124 applyingverification to abstracted design (D′) 144.

Next, the process moves to step 314. At step 314, verificationenvironment 124 determines whether a trace (P′) 152 hitting targets (T)134 has been obtained. If verification environment 124 determines thatno trace was obtained hitting a target, then the process next moves tostep 316, which depicts verification environment 124 propagating targetunhittable results to initial design (D) netlist 120 and reportingresults to output table 122. The process then ends at step 318.

If verification environment 124 determines that abstracted trace (P′)152 is obtained hitting a target (T) 134, then the process next moves tostep 320. At step 320, verification environment 124 copies valuationsfrom set (C′) 176 into new trace (p) 178. The process then proceeds tostep 322, which depicts verification environment 124 propagating newtrace (p) 178 over initial design (D) netlist 120 to the user andreporting results to output table 122. The process then ends at step318.

Given a binary decision diagram 170 representing all possible valuationsto the cut gates (U) 132 (represented as binary decision diagram 170variables G_i) as a function of registers (represented as binarydecision diagram 170 variables R_j), correlating to set S of 304,replacement unit 158 creates the replacement cone in several steps. Notethat gate set (C″) 146 will be a combinational function over a newRANDOM gate for each of the G_i variables, and over the originalregisters R_j. Additionally, the original RANDOM gates do not appear inthe gate set (C″) 146 (unless they are to be preserved). Gate set (C″)146 includes a gate C′_i used to replace each C_i, such that C′_i drivesthe same behavior as C_i as a function of R_j, constructed using themethod embodied in the pseudocode for a Create_Replacement datastructure below, which performs appropriately on binary decisiondiagrams 170 that include inverted edges.

As discussed below, binary decision diagrams 170 variables are referredto as “nonquantifiable” or “quantifiable”. Binary decision diagrams 170variables are created by BDD builder 126 either for cut gates (U) 132(e.g., the G_i variables referred to above), or for RANDOM gates andregisters. The variables for RANDOM gates are most often “quantifiable”(unless they are also G_i variables); the G_i variables and those forregisters are most often “nonquantifiable”. As will be discussed below,certain RANDOM gate variables (which may or may not be cut gates (U) 132themselves) may in cases be deemed “nonquantifiable” if they are to bepreserved. Hence, the present invention is discussed with respect to thequantifiable/nonquantiafiable terminology for generality.

With reference now to FIG. 5, a high-level logical flowchart of aprocess for performing optimal synthesis of binary decision diagramswith inverted edges and quantifiable as well as nonquantifiablevariables in accordance with a preferred embodiment of the presentinvention is illustrated. This flowchart correlates to a description ofthe pseudocode for Create_Replacement to be provided below. The processstarts at step 500 and then proceeds to step 502, which depictsreplacement unit 158 receiving a binary decision diagram 170, hereafterreferred to as B, over quantifiable binary decision diagram 170 variableQ and nonquantifiable BDD variables X, in addition to mapping n(X)between nonquantifiable variables and gates of initial design (D)netlist 120. The process then moves to step 504. At step 504, for eachquantifiable variable q in Q, replacement unit 158 creates a RANDOM gaten(q). The process next proceeds to macro-step 506, which depictsreplacement unit 158 establishing preliminary data structures for B andconsists of steps 508-512.

At step 508, replacement unit 158 traverses each child node of Brecursively from root to leaves, tracking whether an even or an oddnumber of inverted handles were encountered between the root and node b,and neglecting to traverse the children of the same node more than once.The process next moves to step 510, which illustrates, for each node bencountered, if through an even number of inverted handles, replacementunit 158 enqueueing that node in a Vars_To_Nodes(v) storage location.Similarly, for each node b encountered, if through an even number ofinverted handles, replacement unit 158 enqueues the inverse of that nodein a Vars_To_Nodes(v) storage location. The process then proceeds tostep 512. At step 512, for each node b encountered, if the immediateparent of node b had a non-inverted handle, then replacement unit 158sets variable p to that parent. Otherwise, replacement unit 158 sets pto the inverse of that parent. If node b was encountered through an evennumber of inverted handles, then replacement unit 158 enqueues p inParents(v). Otherwise, replacement unit 158 enqueues p inParents_Ivt(v).

The process next moves to macro-step 514, which depicts replacement unit158 iterating over each binary decision diagram 170 variable in rankorder of B (from root to leaf), through a series of steps labeled516-554. At step 516, replacement unit 158 creates a for loop toiteratively repeat macro-step 518, discussed below, for each binarydecision diagram 170 variable v in Q or X, in rank order of B. Theprocess then proceeds to macro-step 518, which illustrates replacementunit 158 building a gate representation of the OR of all parent pathsinto node b, tracking inversions, and storing into path(b) orPath_Ivt(b) accordingly through a series of steps labeled 520-528 andsteps 532-538. At step 520, replacement unit 158 creates a for loop toiteratively repeat steps 522-528 and steps 532-538, discussed below, foreach binary decision diagram 170 node b in Vars_to_Nodes(v). The processnext moves to step 522, which illustrates replacement unit 158determining whether b is the root binary decision diagram 170 node. If bis the root binary decision diagram 170 node, then the process proceedsto step 524, which depicts replacement unit 158 setting variableg=GATE_ONE, after which the process continues to step 526, which isdiscussed below. If b is not the root binary decision diagram 170 node,then the process moves to step 534.

At step 534, replacement unit 158 determines whether b is inverted. If bis inverted, then the process proceeds to step 536, which illustratesreplacement unit 158 setting g equal to a function ‘OR(over all parentnodes b’ In Parents_Ivt(b) of:(inverted(b′)?Path(b′),Path_Ivt(b′0), AND(b is a BDD_THEN branch of b′? r(BDD_VARID(b′)): INVERT (r(BDD_VARID(b′))’. The process then continues to step 526, which is discussedbelow. If b is not inverted, then the process proceeds to step 538,which illustrates replacement unit 158 setting g equal to a function‘OR(over all parent nodes b’ In Parents (b)of:(inverted(b′)?Path(b′),Path_Ivt(b′0), AND (b is a BDD_THEN branch ofb′? r(BDD_VARID(b′)): INVERT (r(BDD_VARID (b′))’. The process thencontinues to step 526.

At step 526, replacement unit 158 determines whether b is inverted. If bis inverted, then the process proceeds to step 528, which illustratesreplacement unit 158 setting Path_Ivt(b)=g. The process then moves tostep 530, which is described below. If b is not inverted, then theprocess proceeds to step 532, which illustrates replacement unit 158setting Path(b)=g. The process then continues to step 530. At step 530,replacement unit 158 determines whether the variable v is quantifiablein Q. If the variable v is quantifiable in Q, then the process nextmoves to step 544, the first step of macro-step 542, which containssteps 544 to 554, and depicts replacement unit 158 creating asynthesized gate for variable v. At step 544, replacement unit 158 setsr(v)=n(v), and the process next proceeds-once iteration over all BDDvariables v in macro-step 514 has completed—to step 556, whichillustrates replacement unit 158 returning n(Q) as the synthesized gatesfor Q binary decision diagram 170 variables. The process then ends atstep 556.

Returning to step 530, if the variable v is not quantifiable in Q, thenthe process next moves step 540 wherein it initializesVar_Must_Be_(—)0(v) to ZERO, and Var_Must Be_(—)1(v) to ZERO. It thenmoves to step 546, which illustrates replacement unit 158 setting a forloop to iterate steps 548-554 over each binary decision diagram 170 nodein Vars_To_Nodes(v). The process next proceeds to step 548. At step 548,replacement unit 158 determines whether b is inverted. If b is inverted,then the process next moves to step 550, replacement unit 158 sets g0=Path_Ivt(b) AND (mux-based-synthesis (BDD_EXIST (BDD_INVERT (BDD_THEN(b), Q)))) and sets g1=Path_Ivt(b) AND (mux-based-synthesis(BDD_EXIST(BDD_INVERT(BDD_ELSE(b), Q)))). The processs then moves to step 552,which depicts replacement unit 158 settingVar_Must_Be_(—)0(v)=Var_Must_Be_(—)0(v) OR NOT(g0); and settingVar_Must_Be_(—)1(v)=Var_Must_Be_(—)1(v) OR NOT (g1); and settingr(v)=Var_Must_Be_(—)1(v) OR (n(v) AND NOT(Var_Must_Be_(—)0(v))). Onceiteration over all BDD variables v in macro-step 514 has completed, theprocess then proceeds to step 556, which is described above.

Returning to step 548, if b is not inverted, then the process moves tostep 554. At step 554, replacement unit 158 sets g0=Path (b) AND(mux-based-synthesis (BDD_EXIST (BDD_INVERT (BDD_THEN (b), Q)))) andsets g1=Path (b) AND (mux-based-synthesis(BDD_EXIST(BDD_INVERT(BDD_ELSE(b), Q)))). The process next returns to step 552,which is described above.

The following legend will be provide assistance in decoding thepseudocode for Create_Replacement below, which represents a preferredembodiment of replacement unit 158 and the method of the flowchart ofFIG. 5:

C_i represents a cut gate (U) 132 from original design (D) netlist 120

G_i: binary decision diagram 170 variables for (quantifiable) cut gates(U) 132

R_j: binary decision diagram 170 variables for nonquantifiable variables(e.g., registers)

n (G_i): netlist RANDOM gate to be used in gate set (C″) 146,correlating to binary decision diagram 170 variable G_i (i.e., toreplace C_i)

n (R_j): netlist gate correlating to nonquantifiable binary decisiondiagram 170 variable R_j (e.g., a register)

r (G_i): replacement gate C′_i created for C_i (note that G_i uniquelycorrelates to a C_i)

r (R_j): netlist gate correlating nonquantifiable BDD variable R_j(e.g., a register gate)

BDD_TOP: the binary decision diagram 170 to be synthesized

BDD_ONE: represents the constant-one binary decision diagram 170

BDD_ZERO: represents the constant-zero binary decision diagram 170

GATE_ONE: represents a constant-one gate

GATE_ZERO: represents a constant-zero gate

BDD_THEN (node): gets the “then” child of binary decision diagram 170node “node”

BDD_ELSE (node): gets the “else” child of binary decision diagram 170node “node”

BDD_INVERT (node): inverts the binary decision diagram 170 node—flippingthe “is inverted” flag

BDD_IS_INVERTED (node): returns ‘1’ exactly when the “is inverted” flagof the binary decision diagram 170 is set

BDD_CLEAR_INVERTED (node): clears the “is inverted” flag of the binarydecision diagram 170

BDD_VARID (node): returns the binary decision diagram 170 variableassociated with “node” (which is undefined only for BDD_ZERO andBDD_ONE)

BDD_EXIST (node, Q): returns a binary decision diagram 170 representing“node” with variables in Q existentially quantified out

OR (a,b): creates an OR gate whose inputs are gates a and b

OR_QUEUE (q): creates an OR gate whose inputs are the gates in queue q

AND (a,b): creates an AND gate whose inputs are gates a and b

AND_QUEUE (q): creates an AND gate whose inputs are the gates in queue q

NOT(a): creates an INVERTER gate whose input is gate a

IF_THEN_ELSE (a,b,c): returns a gate encoding the function (OR (AND(a,b), AND (NOT (a), c)))

The pseudocode below represents a top-level function used to create areplacement gate for each G_i void in a preferred embodiment ofreplacement unit 158: void Create_Replacement(BDD BDD_TOP) {  for (eachvariable G_i)   Create a RANDOM gate, called n(G_i);  // Set up Parentand Var_To_Nodes lists:  Create_Replacement1(BDD_TOP, BDD_ONE, 0);  //traverse both quantifiable and nonquantifiable vars  for (each variableV_i in rank order of BDD_TOP)   // follow order of variables from rootto leaves   Create_Replacement2(V_i);  for (each variable G_i not in thesupport of BDD_TOP) {   replace the corresponding cut gate C_i directlyby n(G_i);   r(G_i) = n(G_i);  } } // this function lists the parent BDDnodes for each node plus its inversion // in queue Parents( ) andParents_Ivt( ) respectively, and lists the BDD nodes // plus “inverted”handles for each variable inside of BDD_TOP in queue Vars_To_Nodes( ) //The parent of the root node (BDD_TOP) is uniquely labeled as BDD_ONEvoid Create_Replacement1(BDD node, BDD parent, bool is_inverted) {  if(node == BDD_ONE || node == BDD_ZERO)   return;  // Make sure node ispositive and incorporate its phase in is_inverted:  if(BDD_IS_INVERTED(node)) {   is_inverted = !is_inverted;   node =BDD_CLEAR_INVERTED(node);   if (parent != BDD_ONE)    parent =BDD_INVERT(parent);  }  if (is_inverted) {   push(Parents_Ivt(node),parent);   push_unique(Vars_To_Nodes(BDD_VARID(node)),BDD_INVERT(node)); // need not push a given BDD handle twice ontoVars_To_Nodes  }  else {   push(Parents(node), parent);  push_unique(Vars_To_Nodes(BDD_VARID(node)), node);  }  if(!visited(node)) {   visited(node) = TRUE;  Create_Replacement1(BDD_THEN(node), node, is_inverted);  Create_Replacement1(BDD_ELSE(node), node, is_inverted);  } } // thisfunction replaces each quantifiable C_i whose G_i is in the support //of BDD_TOP with a trace-equivalent gate void Create_Replacement2(BDD_VARv) {  for (each BDD node in Vars_To_Nodes(v))  Create_Replacement3(node);  if (v is a “quantifiable variable”) {  for (each BDD node in Vars_To_Nodes(v))   Create_Replacement4(node);  // The function to be created is   // must_be_1 OR (n(v) ANDNOT(OR(must_be_0,must_be_1)))   // which simplifies to   // must_be_1 OR(n(v) AND NOT(must_be_0))   must_be_0 = OR_QUEUE(Var_Must_Be_0(v));  must_be_1 = OR_QUEUE(Var_Must_Be_1(v));   random = NOT(must_be_0);  replacement_gate = OR(must_be_1, AND(n(v), random));   replace thecorresponding cut gate C_i by replacement_gate;   r(G_i) =replacement_gate;  } } // this function creates a gate representing thevaluations to n(R_i) and // n(G_i) variables which correlate to pathsfrom the root BDD_TOP to the // present BDD node/its inversion voidCreate_Replacement3(BDD node) {  assert(node != BDD_ONE && node !=BDD_ZERO);  is_inverted = BDD_IS_INVERTED(node);  node =BDD_CLEAR_INVERTED(node);  if (is_inverted)   Path_Ivt(node) =Create_Path(node, is_inverted);  else   Path(node) = Create_Path(node,is_inverted); } // this is a “helper” function for Create_Replacement3.It produces a gate representing the // valuations to gates correlatingto BDD variables higher in the rank which “sensitize” the path // fromthe root BDD_TOP to the present node gate Create_Path(BDD node, boolis_inverted) {  list = is_inverted ? Parents_Ivt(node) : Parents(node); final_gate = GATE_ZERO;  // Note: root node has single BDD_ONE parent.for (each parent in list) {  if (parent == BDD_ONE) {   // this onlyhappens for “root” node   return GATE_ONE;  }  if(BDD_IS_INVERTED(parent)) {   invert2 = !is_inverted;   parent =BDD_CLEAR_INVERTED(parent);   node2 = BDD_INVERT(node);  }  else {  invert2 = is_inverted;   node2 = node;  }  gate = invert2 ?Path_Ivt(parent) : Path(parent);  // We use r(varid) vs. n(varid) toensure that the synthesis is correct and  // preserves the range of thecut. I.e., synthesized functions of lower vars may  // otherwise notreally correlate to values of synthesized functions of higher  // vars,being “misled” by looking at the free parametric var valuations n(varid) // themselves instead of the synthesized functions r(varid) whichreflect  // conditions under which the r(varid) != n(varid)  if(BDD_THEN(parent) == node2)   gate = AND(gate, r(BDD_VARID(parent))); else // BDD_ELSE(parent) == node2   gate = AND(gate,INVERT(r(BDD_VARID(parent))));  final_gate = OR(final_gate, gate); }return final_gate; } // this function augments the gates representingpaths from BDD_TOP to the // current BDD node (or its inversion)recorded in Create_Replacement3, to // reflect the impact of“nonquantifiable variables” below the node being considered // inCreate_Replacement3 void Create_Replacement4(BDD node) {  is_inverted =BDD_IS_INVERTED(node);  node = BDD_CLEAR_INVERTED(node);  // Note: Q isthe set of quantifiable variables:  if (is_inverted) {   gate =Path_Ivt(node);   node2 = BDD_EXIST(BDD_INVERT(BDD_THEN(node)), Q);  } else {   gate = Path(node);   node2 = BDD_EXIST(BDD_THEN(node), Q);  } // The purpose of the following gate_then is to evaluate the conditionsunder  // which the current BDD_VARID's synthesized function cannotevaluate to ‘1’.  // Note: gate_then will be GATE_ZERO if the resut ofBDD_EXIST is  // BDD_ONE - i.e., the corresponding BDD_VARID is allowedto take the value ‘1’.  // Otherwise, gate_then will represent asynthesis of the valuations to the prior  // synthesized cut gatefunctions, and “deeper” non-quantifiable variables,  // for which thecorresponding cut-point may not evaluate to a ‘1’ -  // we thus push theresult onto Var_Must_Be_0  gate_then = AND(gate, Synthesize(node2)); push(Var_Must_Be_0(BDD_VARID(node)), NOT(gate_then));  if (is_inverted)  node2 = BDD_EXIST(BDD_INVERT(BDD_ELSE(node)), Q);  else   node2 =BDD_EXIST(BDD_ELSE(node), Q);  gate_else = AND(gate, Synthesize(node2)); push(Var_Must_Be_1(BDD_VARID(node)), NOT(gate_else)); } // thisperforms a common multiplexor-based synthesis of a BDD // (withoutparameterization) gate Synthesize(BDD node) {  if (node == BDD_ZERO) return GATE_ZERO;  if (node == BDD_ONE)   return GATE_ONE;  is_inverted= BDD_IS_INVERTED(node);  node = BDD_CLEAR_INVERTED(node);  // Checkwhether already synthesized:  gate = Synthesized(node);  if (!gate) {  gate = IF_THEN_ELSE(r(BDD_VARID(node)), // “if” clause  SYNTHESIZE(BDD_THEN(node)), // “then” clause  SYNTHESIZE(BDD_ELSE(node))); // “else” clause   // Remember the gatenetwork that synthesizes this node:   Synthesized(node) = gate;  }  //Correct result for inversion if necessary:  return is_inverted ?NOT(gate) : gate; }

The pseudocode for algorithm Create_Replacement_Alternative belowrepresents an alternative top-level function used to create areplacement gate C′_i for each G_i. Though this pseudocode issufficiently simpler than that of the prior example, it tends to besuboptimal in practice. The reason is the following. Each BDD_EXIST callwill create a new BDD, which is directly synthesized as the replacementgate for the corresponding cut gate using algorithm Synthesize above.While this BDD, and hence the logic of the corresponding replacementgate, may be smaller for variables high in the rank of BDD_TOP than thecorresponding replacement gate using the algorithm Create-Replacement,the corresponding BDD nodes and logic cannot be reused for thereplacement gates of variables lower in the rank of BDD_TOP, overallincreasing the cumulative size of the replacement logic. voidCreate_Replacement_Alternative(BDD BDD_TOP) {  for each quantifiablevariable V_i   n(V_i) = new RANDOM gate  for (each variable G_i in rankorder of BDD_TOP)  // follow order of variables from root to leaves  //quantify every lower-rank cut variable  b_i = BDD_EXISTS(BDD_TOP,{G_{i+1}, ..., G_N});  // forced_0_i represents conditions for which thereplacement gate  of G_i must evaluate to 0  forced_0_i = BDD_NOT(BDD_THEN( b_i ));  // forced_1_i represents conditions for which thereplacement gate  of G_i must evaluate to 1  forced_1_i = BDD_NOT(BDD_ELSE( b_i ));  r(C_i) = OR( SYNTHESIZE( forced_1_i ), AND( n(C_i), NOT(SYNTHESIZE( forced_0_i)); }

Translation unit 168 translates a counterexample trace, such asabstracted trace (P′) 152 obtained over abstracted design (D′) 144 toone consistent with the initial design (D) netlist 120, such asunabstracted trace (P) 154. A “trace”, such as abstracted trace (P′) 152or unabstracted trace (P) 154 is a set of 0,1 logical evaluations tosome of the gates of a design, such as abstracted design (D′) 144 orinitial design (D) netlist 120, respectively, over time. Tracesgenerated by verification environment 124 may be incomplete; e.g.,traces may not illustrate values for certain gates at certain points intime. If a consistent trace is generated by verification environment124, it is assumed that, if verification environment 124 is performingrandom simulation in a manner which applies any trace values present fora RANDOM gate to drive the random simulation stimulus, and anarbitrarily selected constant is chosen for all other stimuli (forRANDOM gate values at time-steps which are not present in the trace),the value generated in random simulation by verification environment 124for any gate in the design must match the value present in the trace (ifit exists). Otherwise, the corresponding trace is consideredinconsistent, not illustrating sufficient data to demonstrate howcertain gates are taking their values. In discussing translation unit168, the value in TRACE for gate G at time I is referred to asTRACE(G,I), which has values 0, 1, or U (where U means “unknown” or “notpresent”).

Abstracted trace (P′) 152 from the abstracted design (D′) 144 includessome values for gates in the fanout-side of the cut, registers in thefanin-side of the cut at cutpoint 140, the cut gates (U) 132 themselves,and the gate set (C″) 146. Abstracted trace (P′) 152 will not includeany values for the combinational/RANDOM gates on the original fanin-sideof the cut at cutpoint 140, which are not included in abstracted design(D′) 144. Translation unit 168 employs a 2-step process to translateabstracted trace (P′) 152 and thereby generate unabstracted trace (P)154, which is consistent with initial design (D) netlist 120.

Translation unit 168 obtains values for all cut gates (U) 132, andregisters in the support of the gate set (C″) 146, for all time-stepspresent in the trace. Note that some gates may be omitted fromabstracted trace (P′) 152, and some may have values missing for certaintime-steps.

Turning now to FIG. 6, a high-level logical flowchart of a process forperforming reversal of the effects of sequential reparameterization ontraces in accordance with a preferred embodiment of the presentinvention is depicted. The process starts at step 600 and moves to step602, which depicts translation unit 168 receiving initial design (D)netlist 120, equal to (C, C′), abstracted design (D′) 144, equal to(C″,C′), trace p′″ over abstracted design (D′) 144, wherein cut gates U132 represents the subset of C which sources edges to set C′ 176 ininitial design (D) netlist 120 and U′ represents the subset of gate setC″ 146 which source edges of set C′ 176 in abstracted design (D′) 144.Step 602 provides the step of receiving the original design, theabstracted design, and the first trace over the abstracted designwherein a set of cut gates denotes a subset of an identified gate set ofthe initial design which sources one or more edges to an initial gateset in the initial design and where a set of corresponding gates denotesa second gate set which sources one or more edges to the initial gateset in the abstracted design. The process then proceeds to step 604,wherein verification environment 124 uses simulation to populate tracep′″. Particularly, verification environment 124 uses simulation topopulate values to corresponding gates (U′) 148 for the necessary lengthof trace p′″, generating a resulting populated abstracted trace p′ 152.The process then moves to step 606.

At step 606, translation unit 168, casts a k-step satisfiability checkto obtain a trace (P″) 150 over (C), witnessing the same sequenceevaluations to cut gates (U) 132, seen at corresponding gates (U′) 148in abstracted trace (P′) 152. The process next proceeds to step 608,which illustrates translation unit 168 concatenating values to (C) fromtrace (P″) with values to (C′) in abstracted trace (P′) 152 to formunabstracted trace (P) 154, demonstrating a hit of the target in initialdesign (D) netlist 120. The process then moves to step 610. At step 610,translation unit 168 returns new trace (p) 178 over initial design (D)netlist 120, corresponding to trace p′″ over abstracted design (D′) 144.Finally, the process ends at step 612.

In a preferred embodiment of the flowchart of FIG. 6, translation unit168 performs using simple recursive simulation, over the gate set (C″)146, using a method described in pseudocode below: for each timestep iin 0 .. length(TRACE)−1 {  for each cut gate G_i {   if( TRACE (G_i,i) == U ) {    TRACE(G_i, i) = Simulate(G_i, i);   }  } } sim_valueSimulate(gate g, unsigned i) {  if (g has been ‘replaced” by anothergate h) {return Simulate(h,i);}  if( TRACE(g,i) != U ) {returnTRACE(g,i);}  if( g is a register) {   if(i==0) {val =Simulate(INIT_VALUE (g), 0);}   else  {val = Simulate(NEXT_STATE(g),i−1);}  }  else if(g is a RANDOM gate) {   val = randomly choose a 0,1value;  }  else { // g is a combinational gate with function F   val =F( return value of Simulate( ) applied to each input   gate to g, fortime i);  }  TRACE(g,i) = val;  return val; }

Translation unit 168 next performs a satisfiability-check over theoriginal logic (from initial design (D) netlist 120) driving the cutgates (U) 132, to compute values to the RANDOM gates in the originalfanin-side of the cut at cutpoint 140 which will produce the samesequence of values from unabstracted trace (P) 154 at cut gates (U) 132,as a function of the register values in that cut at cutpoint 140. Byconstruction, since abstraction to create abstracted trace (P′) 152preserves semantics (even under constraints (B) 160, as discussedbelow), such a sequence does exist in initial design (D) netlist 120.The pseudocode below represents a function used by translation unit 168to obtain a satisfiability check: void Translate_Trace( ) {  gate tosatisfiability_check = GATE_ONE;  for each timestep j in 0..length(TRACE)−1 {   for each cut gate G_i {    ASSERT(TRACE(G_i, j) ! =U);    // note - the prior pseudocode ensured that these will each bedefined    if ( TRACE (G_i, j) = = 1 ) {     gate = Get_Cone (G_i, j);   }    else    gate = NOT(Get_Cone (G_i, j));   }   gate_to_satisfiability_check = AND (gate,gate_to_satisfiability_check)   }   // need an extra pass over allconstraint (B) 160 gates which were not synthesized, in case their conesdid not overlap that of the targets.   // In that case, their semanticimpact on RANDOM gate stimulus may not be reflected in TRACE;   //disjoint cones separately to ensure that the resulting trace satisfiesthose constraints anyway to ensure overall semantic preservation ofconstraints.   for each constraint gate G_i which was not synthesized   gate_to_satisfiability check = AND (Get_Cone (G_i, j),gate_to_satisfiability_check)  }  produce a trace TRACE2 showing how toevaluate gate_to_satisfiability_check to a logical ‘1’.  useAppend_Traces( ) to produce a consistent trace for the original design,completing the trace translation procedure } // this function performs acombinational unfolding of the design to enable a satisfiability-check// to produce a trace showing how the original fanin-side of the cut canproduce the same // sequence of values seen in TRACE to the cut gates inthe abstract design, which is consistent // with the values to theregisters in the gate set (C″) 146 gate Get_Cone (gate g, unsigned i) { if( MAPPING(g,i) ) {return MAPPING(g,i);} // already created thecorresponding unfolded gate  if( TRACE(g,i) == 0 ) {return GATE_ZERO;} if( TRACE(g,i) == 1 ) {return GATE_ONE;}  if( g is a register) {  if(i==0) {val = Get_Cone(INIT_VALUE(g), 0);}   else  {val =Get_Cone(NEXT_STATE(g), i−1);}  }  else if(g is a R2NDOM gate) {   val =Create RANDOM GateQ; // this creates a new RANDOM gate  }  else { // gis a combinational gate of type F   // here, Create_Gate_F creates agate of the same type as F, connecting the i-th input to this   // gateto the result of calling Get_Cone on the ith-input gate to g, at time i  val = Create_Gate_F( return value of Get_Cone applied to each inputgate to g, for time i); } MAPPING(g,i) = val; return val; }Append_Traces( ) {  for each timestep i in 0. .length(TRACE)−1 {   foreach gate g in the replacement cone {    if(TRACE(g,i) == U) {    TRACE(g,i) = TRACE2( MAPPING(g,i), 0 );    }   }  } }

Translation unit 168 uses satisfiability checking over an unfoldedinstance of the sequential problem embodied in abstracted trace (P′) 152to generate a preliminary trace showing values to the originalfanin-side of the cut at cutpoint 140 which drive the same sequence ofvalues seen in the simulated, abstracted trace (P′) 152. Translationunit 168 then “re-folds” that preliminary trace and append it intoTRACE, resulting in an unabstracted trace (P) 154 demonstrating howinitial design (D) netlist 120 drives the same sequence of valuespresent in abstracted trace (P′) 152 to the cut gates (U) 132 and inturn, to all gates in the fanout-side of the cut at cutpoint 140. It isnoteworthy that the trace translation method applied by translation unit168 is applicable whether the overall abstraction process of parametricreduction toolkit 166 processed the cut gates (U) 132 in one step, orincrementally through many steps.

The design of translation unit 168 includes a noteworthy subtlety. Aregister in the original fanin-side of the cut at cutpoint 140 may fallout of the cone in the gate set (C″) 146. For example, say a cut gate(U) 132 g_i is defined as i_i XOR r_i, where i_i is a RANDOM gate andr_i is a register (XOR denotes the exclusive-or function). Abstractionby parametric reduction toolkit 166 may replace this cut gate (U) 132g_i with a new RANDOM gate if, in initial design (D) netlist 120, thereexists some sequence of values to i_i which will allow the cut gate todrive any possible sequence of 0,1 values, regardless of the values tor_i. The first step of trace translation by translation unit 168 willnot assign values to r_i in its simulation, because gate set (C″) 146does not include r_i. However, the second step of trace translation bytranslation unit 168 will require the sequence of values r_i takes toenable translation unit 168 to choose values for i_i which drive thesequence of values seen at the replaced cut gate (U) 132 in abstracteddesign (D′) 144. The Get_Cone pseudocode above solves this problem, byunfolding “through” such registers with unassigned values in TRACE, toenable the satisfiability check to compute the values of such registers.

Exploitation unit 172 enhances the reduction potential of the parametricreduction toolkit 166 by exploiting invariants (N) 164 and constraints(B) 160 present in initial design (D) netlist 120. The semantics ofinvariants (N) 164 and constraints (B) 160 were described above. Aconstraint (B) 160 gate is one which must always evaluate to a logical‘1’ in the verification process. Constraints (B) 160 representvaluations to RANDOM gates and/or registers which are to be“artificially” disallowed by the verification environment 124.

Without the constraint (B) 160, verification environment 124 mightunnecessarily explore such valuations. Exploitation unit 172 uses thepresence of constraints (B) 160 to simplify gate set (C″) 146, and ifpossible, to eliminate the need for an “artificial constraint” bysynthesizing the constraint (B) 160. For example, if a constraint (B)160 evaluates to a ‘1’ exactly when a vector of RANDOM gates evaluatesto even parity, exploitation unit 172 can eliminate the need for aconstraint (B) 160 to enforce such a condition by creating a portion ofgate set (C″) 146 for any one of those RANDOM gates which is not RANDOM,but instead deterministically drives a ‘1’ exactly when the other RANDOMgates in the vector have odd parity (to overall ensure that sink logicof the original gates see a vector which is guaranteed to adhere to evenparity, even without the constraint). However, in other cases, theconstraint (B) 160 cannot be so synthesized.

For example, assume the constraint (B) 160 is of the form: “a given setof registers has even parity AND a given set of RANDOM gates has oddparity”. Exploitation unit 172 simplifies this constraint (B) 160 bysynthesizing the latter part, to ensure that the RANDOM gates, whenreplaced, drive odd parity. Exploitation unit 172 then simplifies theconstraint (B) 160 to “a given set of registers has even parity.”Because replacement unit 158 does not re-encode registers themselves(doing so would risk moving the complexity class of this problem from NPto PSPACE), exploitation unit 172 cannot synthesize away such aconstraint (B) 160 outright, but can indeed work to synthesize aspectsof such a constraint (B) 160 to simplify gate set (C″) 146, and retainonly a simplified constraint (B) 160 thereafter.

Exploitation unit 172 performs simplification of the gate set (C″) 146and constraints (B) 160 in several steps. Recall that selection unit 156labels sinks of a min-cut process to include constraints (B) 160,thereby ensuring that constraints (B) 160 will be in the fanout-side ofcut at cutpoint 140, or on the cut at cutpoint 140 itself. Thoseconstraints (B) 160 that are not combinationally driven by RANDOM gatescannot be readily simplified by selection unit 156 and replacement unit158. Those constraints (B) 160 that are not combinationally driven byRANDOM gates are ignored by replacement unit 158 in the abstractionprocess and semantically preserved (inasmuch as all gates in the fanoutside of the cut at cutpoint 140 are semantically preserved). Thoseconstraints (B) 160 that are combinationally driven by RANDOM gates arecandidates for simplification (regardless of whether they are alsodriven by registers). Alternative embodiments may add such RANDOM-drivenconstraints (B) 160 gates to the cut at cutpoint 140 to abstract, evenif they are not chosen as being on the min-cut at cutpoint 140, toenable further simplifications.

If a constraint (B) 160 gate is on the cut at cutpoint 140, whenanalyzing the language of the cut at cutpoint 140 to form BDD_TOP topass to gate set (C″) 146 creation code in replacement unit 158, BDD_TOPis conjuncted to the binary decision diagrams 170 representing thefunction of the constraint gate F_i over register variables R_i, andoriginal RANDOM gate variables (with a small subtlety, discussed below),forcing conjunction of (F_i==1) onto BDD_TOP. For other non-constraintgates, replacement unit 158 conjuncts in (F_i==G_i), allowing F_i toevaluate to either a 0 or a 1 as consistent with initial design (D)netlist 120. The conjunctive behavior above effectively restrictsBDD_TOP (representing those valuations to C_i that are sensitizable as afunction of R_i) to eliminate any valuations for which the constraint(B) 160 gate does not evaluate to ‘1’. Synthesis methods used byreplacement unit 158 thereafter create gate set (C″) 146, which has beensimplified by the constraint (B) 160. If the resulting constraint (B)160 is a cut gate (U) 132, now driven by gate set (C″) 146, theresulting constraint (B) 160 will evaluate to a constant ‘1’ inabstracted design (D′) 144, because the resulting constraint (B) 160will be replaced by GATE_ONE. Therefore the resulting constraint (B) 160may trivially be removed as a constraint (B) 160 because it has noartificial “constraining power”.

Some constraints (B) 160 have a sequential nature which cannot besynthesized away by replacement unit 158 with the method discussedabove, and exploitation unit 172 ensures that such constraints (B) 160are preserved, rather than allowing them to be discarded by abstraction,and risking a violation of the semantics of the verification problemwith abstracted design (D′) 144. Exploitation unit 172 handles suchconstraints (B) 160, for any constraint (B) 160 gate which is also a cutgate (U) 132, in several steps. First exploitation unit 172 build F_ifor a constraint (B) 160 function over registers and RANDOM gates (withrespect to the original design). Then, exploitation unit 172existentially quantifies away all RANDOM gate variables from F_i. If theresulting quantified F_i is BDD_ONE, then no special treatment isnecessary, because, for all valuations to the registers, there is alegal set of inputs, and the gate set (C″) 146 will properly reflectexactly that set of inputs. Otherwise, exploitation unit 172 replacesthe constraint (B) 160 with a simplified constraint to disallow somevaluations to registers. The original constraint (B) 160 gate itselfwill be driven by GATE_ONE and will be discarded. Exploitation unit 172adds a new constraint (B) 160 to original design (D) netlist 120, whichis a direct synthesis of this quantified F_i (created using methodSynthesize, which is described above).

Exploitation unit 172 further provides means for addressing a subtletyto constraint (B) 160 handling that may require special treatment. Asdiscussed above, parametric reduction toolkit 166 conjuncts BDD_TOP tothe binary decision diagram 170 (hereafter called B_i) representing thefunction of the constraint gate F_i, which is a function of registervariables and RANDOM gate variables. This conjunction in turn will forcethe gate set (C″) 146 created for the corresponding cut to adhere toevaluating any constraints on the cut to be ‘1’. Forcing the gate set(C″) 146 created for the corresponding cut to adhere to evaluating anyconstraints on the cut to be ‘1’ may be excessively aggressive if theB_i includes “dead-end states” (i.e, valuations to registers for whichno legal input stimulus is possible).

In the example above, given a constraint (B) 160 such as “a given set ofregisters has even parity AND a given set of RANDOM gates has oddparity”, the dead-end constraint (B) 160 contained therein is that “agiven set of registers has even parity”. With such constraints (B) 160,exploitation unit 172 will include only the RANDOM-gate-constrainingportion of the constraint (B) 160 (e.g., “a given set of RANDOM gateshas odd parity”) to conjunct to BDD_TOP, and parametric reductiontoolkit 166 will factor out the dead-end constraint portion beforeexploitation unit 172 conjuncts to BDD_TOP.

Exploitation unit 172 executes the behavior described above whenconjuncting the dead-end states to BDD_TOP. Exploitation unit 172 willforce the function of every replacement gate to include the dead-endstates in its support, which may, for example, turn acombinationally-driven original cut gate (U) 132 into asequentially-driven replacement gate. While this transformation does notnecessarily violate the semantics of the verification problem containedin original design (D) netlist 120, the transformation may beparticularly undesirable if, for example, sequential logic is introducedonto an initial-value cone. In such a case, verification environment 124may encounter cyclic definitions when evaluating the initial states ofthe design, (e.g., the initial value of registers R_1 and R_2 may bothbecome ((R_l AND R_2) OR (NOT R_1 AND NOT R_2)), whereas they originallywere GATE_ONE). Exploitation unit 172 handles this condition by firstbuilding the binary decision diagram 170 B_i for the constraint (B) 160,then extracting the dead-end constraints (B) 160 from B_i by setting thefunction B′_i=BDD_EXIST(B_i, RANDOM gate variables).

If the resulting B′_i is not BDD_ONE, then B′_i contains a list of alldead-end states. Exploitation unit 172 next forms B″_i in a series ofsteps:   B″_i = BDD_ZERO.   For each cube of B′_i // a “cube” is a setof min-terms contained in B′_i such that every binary decision diagrams170 variable in the support of the cube evaluates to a single value  B″_i=BDD_OR(B″_i, BDD_COFACTOR (B_i, cube)). //BDD_COFACTOReffectively performs BDD_AND over B_i and cube, then performs BDD_EXISTover variables in the support of cude on the result Exploitation unit172 finally conjuncts the resulting B″_i onto BDD_TOP, instead ofconjuncting B_i onto BDD_TOP.

An invariant (N) 164 gate is similar to a constraint (B) 160 gate inthat it will always be evaluated to a logical ‘1’ by the verificationenvironment 124. Unlike constraints (B) 160, which are generally“artificial” in the sense that verification environment 124 may evaluatethat gate to a logical ‘0’ if not labeled as a constraint (B) 160, aninvariant (N) 164 gate will always evaluate to a ‘1’ by the structure ofthe problem, even if not labeled as an invariant (N) 164. Thisdifference allows a greater degree of flexibility and reductionpotential, thus invariants (N) 164 may be treated differently fromconstraints (B) 160.

Exploitation unit 172 first treats invariant (N) 164 gates in a mannersimilar to constraint (B) 160 gates for obtaining the set of cut gates(U) 132. Exploitation unit 172 labels invariant (N) 164 gates as sinks,placing them on the fanout-side of the cut at cutpoints 140 (or on thecut at cutpoints 140). Exploitation unit 172 may add any invariant (N)164 gates which are combinationally driven by RANDOM gates as cut gates(U) 132, without regard to whether the min-cut solution includes them.However, instead of conjuncting to BDD_TOP the binary decision diagrams170 representing the function of the invariant (N) 164 gate,exploitation unit 172 uses the inverse of the binary decision diagram170 for the invariant (N) 164 gate as a “don't care” against whichexploitation unit 172 may simplify BDD_TOP. Because any valuation in theinverse of the invariant (N) 164 binary decision diagrams 170 cannot beevaluated by the verification environment 124, the exploitation unit 172may freely add or remove any such valuation from BDD_TOP. Note that thedead-end states B′_i of constraints as discussed above may also be usedas “don't cares” because re-application of B″_i as a constraint willdisallow such conditions from being evaluated during verification of theabstracted design.

To additionally preserve the set of invariant (N) 164 valuations toregisters that will never occur (for later methods to exploit),exploitation unit 172 synthesizes invariant (N) 164 binary decisiondiagrams 170 using the procedure given for the constraint (B) 160 binarydecision diagrams 170 above. Note that with constraints (B) 160,exploitation unit 172 translates simplified constraints (B) 160 ratherthan risk violating verification semantics through the abstraction. Incontrast, invariants (N) 164 are “redundant”. Their synthesis isoptional, and their inclusion can be selected by size of the replacementcone or any variety of other metrics.

Turning now to FIG. 4, a high-level logical flowchart of a process forpreservation of constraints during sequential reparameterization inaccordance with a preferred embodiment of the present invention isdepicted. The process starts at step 400 and then proceeds to step 402,which depicts verification environment 124 receiving initial design (D)netlist 120, including targets (T) 134, state elements (R) 136, primaryinputs (I) 138, and constraints (B) 160. The process next moves to step404. At step 404, selection unit 156 identifies cut points 140 for a cut(C, C′) of initial design (D) netlist 120 where (C′) and cut gates (U)132 are supersets of targets (T) 134 and constraints (B) 160, lettingcut gates (U) 132 represent the cut gates sourcing edges from (C) to(C′).

The process then proceeds to step 406, which depicts replacement unit158 computing the relation (S) 142 of values producible to (I, R, U) byexistentially quantifying primary inputs (I) 138 from relation (S) 142,resulting in a relation (S) 142 from state elements (R) 136 to cut gates(U) 132. The process next moves to step 408. At step 408, replacementunit 158 constrains relation (S) 142 to force constraint (B) 160 gatesin cut gates (U) 132, hereafter referred to as constraint gates in cutgates (BU) 180, to evaluate to one. The process then proceeds to step410, which depicts replacement unit 158 evaluating set (B′) 182 fordead-end states. For each constraint (B) 160 gate in constraint gates incut gates (BU) 180, replacement unit 158 computes a constraint b′ inconstraint gates in cut gates (BU) 180 equal to the value of a functionexistentially_quantify inputs(b). If b′ is not tautologically 1, then b′represents a dead-end state of the applicable constraint (B) 160 gate.

The process next proceeds to step 412. At step 412, replacement unit 158calculates the inverse of set (B′) 182 as ‘don't cares’ to simplifyrelation (S) 142. The process then moves to step 414, which depictsreplacement unit 158 synthesizing relation (S) 142, forming gate set(C″) 146. The process then proceeds to step 416. At step 416,replacement unit 158 synthesizes each of cut gates (BU) 180, forming setB′ 182.

The process next proceeds to step 418, which depicts replacement unit158 forming abstracted design (D′) 144 equal to (C″, C′) withconstraints (B) 160 from set (B′) 182 and set (C′) 176. Gates (U′) 148represent the gates in gate set (C″) 146 corresponding to cut gates (U)132 of 404. The process then proceeds to step 420, which depictsverification environment 124 applying verification to abstracted design(D′) 144.

Next, the process moves to step 422. At step 422, verificationenvironment 124 determines whether an abstracted trace (P′) 152 hittingtargets (T) 134 has been obtained. If verification environment 124determines that no such abstracted trace is obtained hitting a target(T) 134, then the process next moves to step 430, which depictsverification environment 124 propagating target unhittable results toinitial design (D) netlist 120 and reporting results to output table122. The process then ends at step 432.

If verification environment 124 determines that abstracted trace (P′)152 is obtained which hit a target (T) 134, then the process next movesto step 424. At step 424, verification environment 124 uses simulationto populate trace values to corresponding gates (U′) for necessarylength (K) to hit targets (T) 134 in abstracted design (D′) 144 anddefines the resulting abstracted trace (P′) 152. The process next movesto step 426, which depicts translation unit 168 casting a k-stepsatisfiability check to obtain a trace (P″) 150 over (C), witnessing thesame sequence of valuations to cut gates (U) 132 seen at correspondinggates (U′) 148 in abstracted trace (P′) 152. The process next moves tostep 428. At step 428, translation unit 168 concatenates values to (C)from trace (P″) with values to (C) from abstracted trace (P′) 152 toform unabstracted trace (P) 154, demonstrating a hit of the target ininitial design (D) netlist 120. The process then ends at step 432.

Bias unit 174 heuristically preserves the “biases” of RANDOM gates,useful if parametric reduction toolkit 166 for reduction is deployedprior to performing random explicit-state evaluation of initial design(D) netlist 120 (e.g., using verification environment 124 to performrandom simulation/emulation or semi-formal verification). It isfrequently important to specify specific biases for RANDOM gates whichdictate the probability with which they will evaluate to a ‘1’. Forexample, a FLUSH type of signal may need to be toggled occasionally toexpose certain design flaws, but an assertion of such a signal to ‘1’may bring initial design (D) netlist 120 back to its reset state. As aresult, users may desire to and verification environment 124 will allowthem to make such an assertion fairly uncommon. However, the majority ofRANDOM gates may be freely toggled without concern for their bias.

Selection of RANDOM gates with biases requiring preservation by biasunit 174 may be done in several ways. For example, bias unit 174 caninclude any RANDOM gates whose biases are within a specified set ofranges. Bias unit 174 can also preserve a user-specified subset; etc.Bias unit 174 preserves the bias of specified nodes in several steps.Bias unit 174 treats RANDOM gates to be preserved in a manner similar tothe treatment of registers by parametric reduction toolkit 166.Selection unit 156 does not include such RANDOM gates to be preserved assources in the min-cut selection process, preventing the min-cut methodfrom attempting to eliminate them. Selection unit 156 naturally willselect cut gates (U) 132 in a manner calculated to attempt to eliminatethe remainder of the RANDOM gates, avoiding any suboptimal min-cutchoices (e.g., yielding a cut which includes 3 RANDOM gates not to bepreserved plus one which is to be preserved, vs. another available cutincluding 3 RANDOM gates not to be preserved).

Bias unit 174 defines the “nonquantifiable variables” in the binarydecision diagram 170-based methods described above in this invention toinclude not only the register variables, but also the RANDOM gatevariables whose biases are to be preserved. Bias unit 174 heuristicallyattains maximal reductions in RANDOM gates through the abstraction,while preserving the influence of those whose biases need to befine-tuned.

With reference now to FIG. 7, a high-level logical flowchart of aprocess for performing heuristic preservation of critical inputs duringsequential reparameterization in accordance with a preferred embodimentof the present invention is illustrated. The process starts at step 700and then moves to step 702, which depicts verification environment 124receiving initial design (D) netlist 120, including targets (T) 134,state elements (R) 136, primary inputs (I) 138 which can be eliminated,and primary inputs (I′) which cannot be eliminated. The process nextmoves to step 704. At step 704, selection unit 156 identifies cut points140 for a cut (C, C′) of initial design (D) netlist 120 where (C′) andcut gates (U) 132 are supersets of targets (T) 134. Gates (U) 132represent the cut gates sourcing edges from (C) to (C′).

The process then proceeds to step 706, which depicts replacement unit158 computing the relation (S) 142 of values producible to (I, I′, R,U), then existentially quantifying primary inputs (I) 138 from relation(S) 142, resulting in a relation (S) 142 from state elements (R) 136 andnonquantifiable primary inputs (I′) 138 to U. The process next moves tostep 708. At step 708, replacement unit 158 synthesizes relation (S)142, forming gate set (C″) 146. The process then proceeds to step 710which depicts replacement unit 158 forming abstracted design (D′) 144equal to (C″, C′) and letting corresponding gates (U′) 148 represent thegates in gate set (C″) 146 corresponding to cut gates (U) 132 inconstraints (B) 160. The process then proceeds to step 712, whichdepicts verification environment 124 applying verification to abstracteddesign (D′) 144.

Next, the process moves to step 714. At step 714, verificationenvironment 124 determines whether an abstracted trace (p′) 154 isobtained which hits target (T) 134. If verification environment 124determines that such a trace has been obtained, then the process nextmoves to step 724, which depicts verification environment 124propagating target unhittable results to initial design (D) netlist 120.The process then ends at step 722.

Returning to step 714, if verification environment 124 determines thatabstracted trace (p′) 154 is obtained which hits target (T) 134, thenthe process next moves to step 716, which illustrates verificationenvironment 124 copying valuations to set C′ 176 into new trace (p) 178.The process then proceeds to step 718. At step 718, verificationenvironment 124 propagates new trace (p) 178 over initial design (D)netlist 120 to the user through output table 122. The process then endsat step 722.

Turning now to FIG. 2, a high-level logical flowchart of a process forparametric reduction of sequential designs is depicted. The processstarts at step 200 and then proceeds to step 202, which depictsverification environment 124 receiving initial design (D) netlist 120,including targets (T) 134, state elements (R) 136 and primary inputs (I)138. The process next moves to step 204. At step 204, selection unit 156identifies cut points 140 for a cut (C, C′) of initial design (D)netlist 120 where (C′) is a superset of targets (T) 134. Gates (U) 132represent the cut gates sourcing edges from (C) to (C′). The processthen proceeds to step 206, which depicts replacement unit 158 computingthe relation (S) 142 of values producible to (I, R, U). The process thenmoves to step 208.

At step 208, replacement unit 158 synthesizes relation (S) 142, forminggate set (C″) 146. The process proceeds to step 210 which depictsreplacement unit 158 forming abstracted design (D′) 144 equal to (C″,C′). Gates (U′) 148 represent the gates in gate set (C″) 146corresponding to cut gates (U) 132 in constraints (B) 160. The processthen proceeds to step 212, which depicts verification environment 124applying verification to abstracted design (D′) 144.

Next, the process moves to step 214. At step 214, verificationenvironment 124 determines whether trace (P′) 152 has been obtainedwhich hits target (T) 134. If verification environment 124 determinesthat no such trace has been obtained, then the process next moves tostep 216, which depicts verification environment 124 propagating targetunhittable results to initial design (D) netlist 120. The process thenends at step 218.

If verification environment 124 determines that abstracted trace (P′)152 has been obtained which hits target (T) 134, then the process nextmoves to step 220. At step 220, verification environment 124 usessimulation to populate trace values to corresponding gates (U′) fornecessary length (K) to hit targets (T) 134 in (D′) in abstracted design(D′) 144 and defines the resulting abstracted trace (P′) 152. Theprocess next moves to step 222, which depicts translation unit 168,casting a case step satisfiability program to obtain a trace (P″) 150over (C), witnessing the same sequence evaluations to cut gates (U) 132,seen at corresponding gates (U′) 148 in abstracted trace (P′) 152. Theprocess next moves to step 224. At step 224, translation unit 168concatenates values to (C′) and trace (P″) with values to (C) inabstracted trace (P′) 152 to form unabstracted trace (P) 154,demonstrating hit of target in initial design (D) netlist 120. Theprocess then ends at step 218.

While the invention has been particularly shown as described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention. Itis also important to note that although the present invention has beendescribed in the context of a fully functional computer system, thoseskilled in the art will appreciate that the mechanisms of the presentinvention are capable of being distributed as a program product in avariety of forms, and that the present invention applies equallyregardless of the particular type of signal bearing media utilized toactually carry out the distribution. Examples of signal bearing mediainclude, without limitation, recordable type media such as floppy disksor CD ROMs and transmission type media such as analog or digitalcommunication links.

1. A method for reducing sequential digital designs, said methodcomprising: receiving an initial design including one or more primaryinputs, one or more targets, and one or more state elements; identifyinga cut of said initial design including one or more cut gates; computinga relation of one or more values producible to said one or more cutgates in terms of said one or more primary inputs and said one or morestate elements; synthesizing said relation to form a gate set; formingan abstracted design from said gate set; and performing verification onsaid abstracted design to generate verification results.
 2. The methodof claim 1, further comprising: determining whether said step ofperforming verification hit one or more targets; and in response todetermining that said step of performing verification did not hit one ormore targets, propagating one or more target unhittable results to saidinitial design.
 3. The method of claim 1, further comprising:determining whether said step of performing verification hit one or moretargets; and in response to determining that said step of performingverification hit one or more targets copying one or more valuations toan initial gate set into a new trace.
 4. The method of claim 3, furthercomprising: in response to determining that said step of performingverification hit one or more targets propagating said new trace oversaid initial design to a user.
 5. The method of claim 3, wherein saidstep of identifying said cut of said initial design including said oneor more cut gates further comprises: identifying said cut of saidinitial design including said one or more cut gates where said cut gatessource edges from said initial gate set to said second gate set.
 6. Themethod of claim 1, wherein said step of computing said relation of saidone or more values producible to said one or more state elements at saidone or more cut gates in terms of said one or more primary inputsfurther comprises: computing a relation from said state elements to saidcut gates.
 7. The method of claim 1, wherein said step of computing saidrelation of said one or more values producible to said one or more stateelements at said one or more cut gates in terms of said one or moreprimary inputs further comprises: existentially quantifying said primaryinputs from said relation.
 8. A system for reducing sequential digitaldesigns, said system comprising: means for receiving an initial designincluding one or more targets, one or more primary inputs, and one ormore state elements; means for identifying a cut of said initial designincluding one or more cut gates; means for computing a relation of oneor more values producible to said one or more cut gates in terms of saidone or more primary inputs and said one or more state elements; meansfor synthesizing said relation to form a gate set; means for forming anabstracted design from said gate set; and means for performingverification on said abstracted design to generate verification results.9. The system of claim 8, further comprising: means for determiningwhether said means for performing verification hit one or more targets;and means for, in response to determining that said means for performingverification did not hit one or more targets, propagating one or moretarget unhittable results to said initial design.
 10. The system ofclaim 8, further comprising: means for determining whether said meansfor performing verification hit one or more targets; and means for, inresponse to determining that said means for performing verification hitone or more targets, copying one or more valuations to an initial gateset into a new trace.
 11. The system of claim 10, further comprising:means for, in response to determining that said means for performingverification hit one or more targets, propagating said new trace oversaid initial design to a user.
 12. The system of claim 10, wherein saidmeans for identifying said cut of said initial design including said oneor more cut gates further comprises: means for identifying said cut ofsaid initial design including said one or more cut gates where said cutgates source edges from said initial gate set to said second gate set.13. The system of claim 8, wherein said means for computing saidrelation of said one or more values producible to said one or more stateelements at said one or more cut gates in terms of said one or moreprimary inputs further comprises: means for computing a relation fromsaid state elements to said cut gates.
 14. The system of claim 8,wherein said means for computing said relation of said one or morevalues producible to said one or more state elements at said one or morecut gates in terms of said one or more primary inputs further comprises:means for existentially quantifying said primary inputs from saidrelation.
 15. A computer program product in a computer-readable mediumfor reducing sequential digital designs, said computer program productin a computer-readable medium comprising: a computer-readable medium;instructions on the computer-readable medium for receiving an initialdesign including one or more targets, one or more primary inputs, andone or more state elements; instructions on the computer-readable mediumfor identifying a cut of said initial design including one or more cutgates; instructions on the computer-readable medium for computing arelation of one or more values producible to said one or more cut gatesin terms of said one or more primary inputs and said one or more stateelements; instructions on the computer-readable medium for synthesizingsaid relation to form a gate set; instructions on the computer-readablemedium for forming an abstracted design from said gate set; andinstructions on the computer-readable medium for performing verificationon said abstracted design to generate verification results.
 16. Thecomputer program product in a computer-readable medium of claim 15,further comprising: instructions on the computer-readable medium fordetermining whether said instructions on the computer-readable mediumfor performing verification hit one or more targets; and instructions onthe computer-readable medium for, in response to determining that saidinstructions on the computer-readable medium for performing verificationdid not hit one or more targets, propagating one or more targetunhittable results to said initial design.
 17. The computer programproduct in a computer-readable medium of claim 15, further comprising:instructions on the computer-readable medium for determining whethersaid instructions on the computer-readable medium for performingverification hit one or more targets; and instructions on thecomputer-readable medium for, in response to determining that saidinstructions on the computer-readable medium for performing verificationhit one or more targets, copying one or more valuations to an initialgate set into a new trace.
 18. The computer program product in acomputer-readable medium of claim 17, further comprising: instructionson the computer-readable medium for, in response to determining thatsaid instructions on the computer-readable medium for performingverification hit one or more targets propagating said new trace oversaid initial design to a user.
 19. The computer program product in acomputer-readable medium of claim 17, wherein said instructions on thecomputer-readable medium for identifying said cut of said initial designincluding said one or more cut gates further comprise: instructions onthe computer-readable medium for identifying said cut of said initialdesign including said one or more cut gates where said cut gates sourceedges from said initial gate set to said second gate set.
 20. Thecomputer program product in a computer-readable medium of claim 15,wherein said instructions on the computer-readable medium for computingsaid relation of said one or more values producible to said one or morestate elements at said one or more cut gates in terms of said one ormore primary inputs further comprise: instructions on thecomputer-readable medium for computing a relation from said stateelements to said cut gates.